The present invention relates generally to store caches, and more particularly to evicting cached stores based on store pressure.
A computer processor can handle stores at a very high rate. The high store rate is bandwidth limited at the interface between an L2 level cache and an L3 level cache. To reduce the effects of a limited bandwidth, stores are cached between a load store unit (LSU) and the L2 level cache in a store cache. Multiple stores are collected in the store cache prior to being executed to the next lower cache level (i.e., L2 level cache and L3 level cache). The length of time a store resides in the store cache prior to being evicted is determined by a variety of factors. Typically, touch information and time are two criteria used to determine evictions of stores.